// シフトレジスタ シミュレーション記述

`timescale 1ps/1ps

module sftreg_tp;
reg             ck, res, en, si;
wire    [3:0]   q;

parameter STEP = 100000;

always #(STEP/2) ck = ~ck;

shift4 shift4( ck, res, en, si, q );

initial begin
            ck = 0; res = 0; en = 0; si = 0;
    #STEP   res = 1;
    #STEP   res = 0;  
    #STEP   en = 1; si = 1;
    #STEP   si = 0;
    #STEP   si = 1;
    #STEP   si = 0;
    #STEP   en = 0;
    #(STEP*4)
            $finish;
end

initial $monitor( $stime, " ck=%b res=%b en=%b si=%b q=%b",
    ck, res, en, si, q);

endmodule