// 交通信号機のシミュレーション記述

`timescale 1s / 1s

module sim;

	reg clock, reset;

	parameter STEP = 30;

	always #(STEP/2) clock = ~clock;

	traffic_lights traffic_lights( clock, reset );

	initial
		begin
			#0 	clock = 0; reset = 1;
			#STEP	reset = 0;
			#(STEP*80)
            	#STEP	$finish;
		end
  
endmodule