`timescale 1ns/1ns

module gate_tp;

reg in0, in1, in2;
wire out_not, out_and2, out_or3;
parameter STEP = 100;

//論理式によるゲート
gate_ex gate_ex_instance(in0, in1, in2, out_not, out_and2, out_or3);

initial begin
	$dumpfile("gate_tp.vcd");
	$dumpvars(1, gate_tp);
	$monitor($stime, "in0 = %b in1 = %b in2 = %b not = %b and2 = %b or3 =%b", in0, in1, in2, out_not, out_and2, out_or3);
 
    #0      in0 = 0; in1 = 0; in2 = 0;
    #STEP   in0 = 1; in1 = 0; in2 = 0;
    #STEP   in0 = 0; in1 = 1; in2 = 0;
    #STEP   in0 = 1; in1 = 1; in2 = 0;
    #STEP   in0 = 0; in1 = 0; in2 = 1;
    #STEP   in0 = 1; in1 = 0; in2 = 1;
    #STEP   in0 = 0; in1 = 1; in2 = 1;
    #STEP   in0 = 1; in1 = 1; in2 = 1;
    #STEP   $finish;
end

endmodule