`timescale 1ns / 1ps
module TestBench;
// Inputs
reg CLK;
reg RESET;
reg START;

// Outputs
wire [1:0] LED;
 
// Instantiate the Unit Under Test (UUT)
SimpleFSM uut (
	.CLK(CLK),
	.RESET(RESET), 
	.START(START),
	.LED(LED)
);

always 
	#5 CLK = ~CLK; // clock generation
 
initial begin
	//$dumpfile("fsm_sim.vcd"); 
	//$dumpvars(0,TestBench);

	// Initialize Inputs
	CLK = 0;
	RESET = 0;
	START = 0;
	// Wait 50 ns for global reset to finish
	#50;
	// Add stimulus here
	#10 RESET = 1;
	#10 RESET = 0;
	#10 START = 1;
	#20 START = 0;
	#50;
	#10 START = 1;
	#20 START = 0;
	#100 $stop;
end
	
endmodule