ON_Circuit Project Status (01/25/2013 - 16:28:43)
Project File: ON_Circuit.xise Parser Errors: No Errors
Module Name: ON_Circuit Implementation State: Programming File Generated
Target Device: xc3s100e-5cp132
  • Errors:
 
Product Version:ISE 14.2
  • Warnings:
 
Design Goal: Balanced
  • Routing Results:
All Signals Completely Routed
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
 
Environment: System Settings
  • Final Timing Score:
0  (Timing Report)
 
Device Utilization Summary [-]
Logic UtilizationUsedAvailableUtilizationNote(s)
    Number of Slices containing only related logic 0 0 0%  
    Number of Slices containing unrelated logic 0 0 0%  
Number of bonded IOBs 2 83 2%  
Average Fanout of Non-Clock Nets 1.00      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints:      
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrent金 1 25 16:25:03 2013000
Translation ReportCurrent金 1 25 16:28:15 2013000
Map ReportCurrent金 1 25 16:28:21 2013   
Place and Route ReportCurrent金 1 25 16:28:26 2013001 Info (1 new)
Power Report     
Post-PAR Static Timing ReportCurrent金 1 25 16:28:29 2013006 Infos (6 new)
Bitgen ReportCurrent金 1 25 16:28:33 2013000
 
Secondary Reports [-]
Report NameStatusGenerated
WebTalk ReportCurrent金 1 25 16:28:33 2013
WebTalk Log FileCurrent金 1 25 16:28:43 2013

Date Generated: 01/25/2013 - 16:28:43