Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
 

 
Software Version and Target Device
Product Version: ISE:14.2 (ISE) - P.28xd Target Family: Spartan3E
OS Platform: NT64 Target Device: xc3s100e
Project ID (random number) 3da47eb8922b46d895099619ad7cc70e.8C155DD8492D418899885695E60B34B7.1 Target Package: cp132
Registration ID 208275516_208276933_208889692_349 Target Speed: -5
Date Generated 2013-01-25T16:28:33 Tool Flow ISE
 
User Environment
OS Name Microsoft Windows 7 , 64-bit OS Release Service Pack 1 (build 7601)
CPU Name Intel(R) Core(TM) i7-2600 CPU @ 3.40GHz CPU Speed 3392 MHz
 
Device Usage Statistics
Macro StatisticsMiscellaneous StatisticsNet StatisticsSite Usage
  MiscellaneousStatistics
  • AGG_BONDED_IO=2
  • AGG_IO=2
  • NUM_BONDED_IBUF=1
  • NUM_BONDED_IOB=1
NetStatistics
  • NumNets_Active=3
  • NumNodesOfType_Active_DOUBLE=2
  • NumNodesOfType_Active_DUMMYESC=1
  • NumNodesOfType_Active_HUNIHEX=1
  • NumNodesOfType_Active_INPUT=1
  • NumNodesOfType_Active_IOBOUTPUT=1
  • NumNodesOfType_Active_VFULLHEX=2
  • NumNodesOfType_Active_VUNIHEX=1
SiteStatistics
  • IOB-DIFFM=1
SiteSummary
  • IBUF=1
  • IBUF_INBUF=1
  • IBUF_PAD=1
  • IOB=1
  • IOB_OUTBUF=1
  • IOB_PAD=1
 
Configuration Data
IBUF_PAD
  • IOATTRBOX=[LVCMOS25:1]
IOB
  • O1=[O1_INV:0] [O1:1]
IOB_OUTBUF
  • IN=[IN_INV:0] [IN:1]
IOB_PAD
  • DRIVEATTRBOX=[12:1]
  • IOATTRBOX=[LVCMOS25:1]
  • SLEW=[SLOW:1]
 
Pin Data
IBUF
  • I=1
  • PAD=1
IBUF_INBUF
  • IN=1
  • OUT=1
IBUF_PAD
  • PAD=1
IOB
  • O1=1
  • PAD=1
IOB_OUTBUF
  • IN=1
  • OUT=1
IOB_PAD
  • PAD=1
 
Tool Usage
Command Line History
  • xst -intstyle ise -ifn <ise_file>
  • ngdbuild -intstyle ise -dd _ngo -nt timestamp -uc <fname>.ucf -p xc3s100e-cp132-5 <fname>.ngc <fname>.ngd
  • map -intstyle ise -p xc3s100e-cp132-5 -cm area -ir off -pr off -c 100 -o <fname>.ncd <fname>.ngd <fname>.pcf
  • par -w -intstyle ise -ol high -t 1 <fname>.ncd <fname>.ncd <fname>.pcf
  • trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml <fname>.twx <fname>.ncd -o <fname>.twr <fname>.pcf -ucf <fname>.ucf
  • bitgen -intstyle ise -f <fname>.ut <fname>.ncd
 
Software Quality
Run Statistics
Program NameRuns StartedRuns FinishedErrorsFatal ErrorsInternal ErrorsExceptionsCore Dumps
_impact 5 5 0 0 0 0 0
bitgen 54 53 0 0 0 0 0
edif2ngd 19 18 0 0 0 0 0
elfcheck 234 234 0 0 0 0 0
libgen 44 43 0 0 0 0 0
map 65 59 0 0 0 0 0
ngc2edif 142 142 0 0 0 0 0
ngcbuild 167 167 0 0 0 0 0
ngdbuild 71 69 0 0 0 0 0
par 61 59 2 0 0 0 0
platgen 49 45 0 0 0 0 0
psf2Edward 29 29 0 0 0 0 0
trce 59 59 0 0 0 0 0
xdsgen 26 26 0 0 0 0 0
xps 111 45 0 0 0 0 0
xst 474 472 0 0 0 0 0
 
Project Statistics
PROP_Enable_Message_Filtering=false PROP_FitterReportFormat=HTML
PROP_LastAppliedGoal=Balanced PROP_LastAppliedStrategy=Xilinx Default (unlocked)
PROP_ManualCompileOrderImp=false PROP_PropSpecInProjFile=Store all values
PROP_Simulator=ISim (VHDL/Verilog) PROP_SynthTopFile=changed
PROP_Top_Level_Module_Type=HDL PROP_UseSmartGuide=false
PROP_UserConstraintEditorPreference=Text Editor PROP_intProjectCreationTimestamp=2013-01-25T16:23:02
PROP_intWbtProjectID=8C155DD8492D418899885695E60B34B7 PROP_intWbtProjectIteration=1
PROP_intWorkingDirLocWRTProjDir=Same PROP_intWorkingDirUsed=No
PROP_lockPinsUcfFile=changed PROP_AutoTop=true
PROP_DevFamily=Spartan3E PROP_DevDevice=xc3s100e
PROP_DevFamilyPMName=spartan3e PROP_DevPackage=cp132
PROP_Synthesis_Tool=XST (VHDL/Verilog) PROP_DevSpeed=-5
PROP_PreferredLanguage=Verilog FILE_UCF=1
FILE_VERILOG=1
 
Unisim Statistics
NGDBUILD_PRE_UNISIM_SUMMARY
NGDBUILD_NUM_IBUF=1 NGDBUILD_NUM_OBUF=1
NGDBUILD_POST_UNISIM_SUMMARY
NGDBUILD_NUM_IBUF=1 NGDBUILD_NUM_OBUF=1
 
XST Command Line Options
XST_OPTION_SUMMARY
-ifn=<fname>.prj -ifmt=mixed -ofn=<design_top> -ofmt=NGC
-p=xc3s100e-5-cp132 -top=<design_top> -opt_mode=Speed -opt_level=1
-iuc=NO -keep_hierarchy=No -netlist_hierarchy=As_Optimized -rtlview=Yes
-glob_opt=AllClockNets -read_cores=YES -write_timing_constraints=NO -cross_clock_analysis=NO
-bus_delimiter=<> -slice_utilization_ratio=100 -bram_utilization_ratio=100 -verilog2001=YES
-fsm_extract=YES -fsm_encoding=Auto -safe_implementation=No -fsm_style=LUT
-ram_extract=Yes -ram_style=Auto -rom_extract=Yes -shreg_extract=YES
-rom_style=Auto -auto_bram_packing=NO -resource_sharing=YES -async_to_sync=NO
-mult_style=Auto -iobuf=YES -max_fanout=500 -bufg=24
-register_duplication=YES -register_balancing=No -optimize_primitives=NO -use_clock_enable=Yes
-use_sync_set=Yes -use_sync_reset=Yes -iob=Auto -equivalent_register_removal=YES
-slice_utilization_ratio_maxmargin=5