| ON_Circuit Project Status (01/25/2013 - 16:28:43) | |||
| Project File: | ON_Circuit.xise | Parser Errors: | No Errors |
| Module Name: | ON_Circuit | Implementation State: | Programming File Generated |
| Target Device: | xc3s100e-5cp132 |
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| Product Version: | ISE 14.2 |
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| Design Goal: | Balanced |
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All Signals Completely Routed |
| Design Strategy: | Xilinx Default (unlocked) |
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| Environment: | System Settings |
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0 (Timing Report) |
| Device Utilization Summary | [-] | ||||
| Logic Utilization | Used | Available | Utilization | Note(s) | |
| Number of Slices containing only related logic | 0 | 0 | 0% | ||
| Number of Slices containing unrelated logic | 0 | 0 | 0% | ||
| Number of bonded IOBs | 2 | 83 | 2% | ||
| Average Fanout of Non-Clock Nets | 1.00 | ||||
| Performance Summary | [-] | |||
| Final Timing Score: | 0 (Setup: 0, Hold: 0) | Pinout Data: | Pinout Report | |
| Routing Results: | All Signals Completely Routed | Clock Data: | Clock Report | |
| Timing Constraints: | ||||
| Detailed Reports | [-] | |||||
| Report Name | Status | Generated | Errors | Warnings | Infos | |
| Synthesis Report | Current | 金 1 25 16:25:03 2013 | 0 | 0 | 0 | |
| Translation Report | Current | 金 1 25 16:28:15 2013 | 0 | 0 | 0 | |
| Map Report | Current | 金 1 25 16:28:21 2013 | ||||
| Place and Route Report | Current | 金 1 25 16:28:26 2013 | 0 | 0 | 1 Info (1 new) | |
| Power Report | ||||||
| Post-PAR Static Timing Report | Current | 金 1 25 16:28:29 2013 | 0 | 0 | 6 Infos (6 new) | |
| Bitgen Report | Current | 金 1 25 16:28:33 2013 | 0 | 0 | 0 | |
| Secondary Reports | [-] | ||
| Report Name | Status | Generated | |
| WebTalk Report | Current | 金 1 25 16:28:33 2013 | |
| WebTalk Log File | Current | 金 1 25 16:28:43 2013 | |