Adder4 Project Status (04/01/2013 - 16:45:29)
Project File: Display7SEG.xise Parser Errors: No Errors
Module Name: Adder4 Implementation State: Programming File Not Generated
Target Device: xc3s100e-5cp132
  • Errors:
  
Product Version:ISE 14.2
  • Warnings:
  
Design Goal: Balanced
  • Routing Results:
  
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
  
Environment:  
  • Final Timing Score:
   
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis Report     
Translation Report     
Map Report     
Place and Route Report     
CPLD Fitter Report (Text)     
Power Report     
Post-PAR Static Timing Report     
Bitgen Report     
 
Secondary Reports [-]
Report NameStatusGenerated
ISIM Simulator LogOut of DateŒŽ 4 1 16:06:45 2013
WebTalk ReportCurrentŒŽ 4 1 16:45:13 2013
WebTalk Log FileCurrentŒŽ 4 1 16:45:17 2013

Date Generated: 04/01/2013 - 16:45:29